FPGA HINTS, TIPS, AND TRICKS

FPGA HINTS, TIPS, AND TRICKS

Peter Safir

Bachelor of Science, The Azrieli College of Engineering in Jerusalem (JCE),

Israel, Jerusalem

ABSTRACT

It is not always necessary to write long code. Most of the time there are workarounds when programming on an FPGA and in most cases many logic functions can be implemented in a very easy and short way. In this article I would like to present some easy solutions for the FPGA. I will give the options to reduce the input frequency based on a flip flop. We will also look at multiplication and division with a degree of two with a logical shift.

Keywords: FPGA, RTL, flip flop, frequency division, PLL, logical shift, multiplication, division, debouncing.

Introduction

Implementing FPGA [1] projects is not an easy task, requiring a deep knowledge of electronics and a lot of time. But it is not always the case that when writing FPGA code, we don't need to create long code to accomplish our goals. In many cases, the right approach allows us to use some workarounds to get the project done quickly.

Frequency Division

There are several ways to create a frequency on the FPGA. You can do it with the PLL wizard, or you can do it with a counter based on a timer. The main problem with PLLs is that they are limited and not always have enough channels to generate them. Sometimes you can take the frequency generated by PLL [2] to reduce it without using FPGA resources. There are several ways to reduce frequency with degree two, but the simplest and not requiring significant changes in code and using lots of FPGA resources is to create a frequency divider via triggers. D flip flop[3] can be used as a frequency divider of the incoming frequency by two. In figure 1.1 we see a connection diagram for a D flip flop to form a frequency at the output Q which is half the frequency of the input frequency. As input we use the inverted output Q' with the D flip flop, creating a feedback. Thus we see that the output Q forms a frequency which is exactly half of the input clock frequency.

Figure 1.1. D flip flop

It is also possible to create a D flip flop network (Figure 1.2) where the incoming frequency divisions will be decreased by two with each subsequent D flip flop output.

Figure 1.2. D flip flop network

Frequency doubles

We do not always need to decrease the input frequency. In some cases we need to increase the frequency without using a PLL. This scheme (Figure 1.3)allows to increase the input frequency by a factor of two. It is easy to implement this circuit in any FPGA language such as VHDL, Verilog[4].

Figure 1.3 Frequency doubles

Multiplication and Division by Logical Shift

With logical shift[5] it is easy to multiply by powers of two without using almost any FPGA resources, and the execution speed is much faster than with any other algorithms.

Logical Shift

A left logical shift shifts each bit one position to the left whereby the most significant bit (MSB) is discarded and a zero is added to the least significant bit (LSB).

Figure 1.4 A left logical shift

A right logical shift shifts each bit to the right by one position, adding a zero to the high bit (MSB) and discarding the low bit (LSB).

Figure 1.5 A right logical shift

Multiplication by left shift

The left logical shift will result in multiplication[6] by . n- is the number of bits by which the left shift occurred. For example if we shift to the left 0010 = 2 we get 0100 which in decimal system equals 4, then one more left shift and we get 1000 = 8.

Division by right shift

The right logical shift will divide by . n- is the number of bits by which the right shift occurs. For example if we shift 1010 = 10 one bit to the right we get 0101 which is 5 in decimal.

Debouncing

Figure 1.6 debouncing

When any mechanical switches [7] are switched, they create contact bounce. The circuit in figure 1. 6, uses feedback to suppress debouncing. It is necessary to set the current on the pin where the switch is connected to a minimum to reduce the current spikes when switching.

Conclusion

As we see there are some ways to help us significantly reduce the development time [8] and also to save FPGA resources. Not every project can use these methods.

References:

1. VHDL: Programming By Example 4th Edition. Douglas Perry. McGraw-Hill Education. June 2, 2002. P 89 – 102.
2. Circuit Design with VHDL. Volnei A. Pedro. The MIT Press April 14, 2020. P. 28 – 39.
3. Effective Coding with VHDL: Principles and Best Practice. Ricardo Jasinski. The MIT Press May 27, 2016. P 56 – 78.
4. Digital Design. M. Morris Mano, Morris M Mano. Prentice Hall. January 1, 2001. P. 102 – 1115.
5. Digital Design: With an Introduction to the Verilog HDL, VHDL, and System Verilog.  M. Morris Mano, Michael Ciletti. Pearson. March 7, 2017. P. 59 – 67.
6. Digital Design: A Systems Approach. William James Dally, R. Curtis Harting. Cambridge University Press. 01 Nov 2012. P. 45 – 66.
7. Introduction to Logic Circuits & Logic Design with Verilog. Brock J. LaMeres. Springer. October 2, 2020. P. 120 – 133.
8. Digital Design and Computer Architecture. David Harris, Sarah L. Harris. Morgan Kaufmann. August 7, 2012. P. 35 – 40.